With the increasing down-scaling of integrated circuits (IC) and increasingly demanding requirements to the speed of ICs, transistors need to have higher drive currents with increasingly smaller dimensions. Fin field-effect transistors (FinFET) were thus developed. In a typical finFET, portions of a substrate are etched away to create a vertical fin structure. This vertical fin structure is used to form source/drain regions in the lateral direction, forming a channel region in the fin. A gate is formed over channel region of the fin in the vertical direction forming a finFET. Subsequently, an inter-layer dielectric (ILD) and a plurality of interconnect layers may be formed over the finFET. The ILD includes gate contacts electrically connecting the gate to other active components in the IC through the plurality of interconnect layers.
The gate contacts are generally narrower in width than the gate; therefore, the gate contact area may be relatively small. A small gate contact area creates high contact resistance between the gate and the gate contact. Unfortunately, due to design rule limitations, the width of the gate contact is not easily increased or adjusted.